The email that NASA’s engineering team sent in February 2026 when they powered up the new processor for the first time had a subject line that said everything about the ambition behind it: “Hello Universe.” The chip they were testing, formally called the High Performance Spaceflight Computing processor, or HPSC, is designed to do something that no spacecraft computer has ever been capable of doing reliably: think. Not in the way science fiction imagines thinking machines, but in the precise, consequential sense that matters most for the future of space exploration. When a spacecraft is traveling hundreds of millions of miles from Earth, when a radio signal takes 20 minutes to travel in each direction, and when a split-second autonomous decision could mean the difference between a successful landing and a crater, the ability of the space chip on board to process, reason, and act without waiting for human input becomes a mission-critical capability rather than a luxury.
The early results from testing at NASA’s Jet Propulsion Laboratory have been striking. The processor is delivering approximately 100 times the computational capacity of the spaceflight computers currently in use, with some benchmark tests suggesting performance levels approaching 500 times current hardware in specific workloads. For a technology domain where meaningful improvements have historically been measured in single-digit percentages constrained by radiation tolerance requirements, those numbers represent a generational leap.
Why Spacecraft Still Run on Ancient Chips
The first thing most people find surprising about the HPSC announcement is that it was necessary at all. NASA has some of the most sophisticated engineering capabilities on Earth. Why, in 2026, are its spacecraft still running on processors developed years or decades ago?
The answer is radiation. The space environment is hostile to electronics in ways that have no terrestrial equivalent. High-energy particles from the sun and from interstellar space continuously bombard spacecraft, penetrating the processor and flipping individual bits from zero to one or from one to zero, a phenomenon called a single-event upset. On Earth, with radiation levels thousands of times lower, this happens rarely enough that modern computing infrastructure can ignore it. In deep space, it happens constantly. An unprotected consumer-grade processor in deep space would accumulate errors faster than any software could correct them, causing system crashes, data corruption, and potential mission failure.
Building a radiation-hardened processor, one that detects and corrects these bit-flip errors in real time without losing data or crashing, requires design choices that fundamentally constrain performance. The transistors must be physically larger to reduce their vulnerability to particle strikes. Redundant circuits must be added to catch and correct errors. Memory systems must implement error-correction codes that add computational overhead. The result is a processor that is extraordinarily reliable in an environment that destroys ordinary electronics, but that sacrifices the performance density that has driven the commercial semiconductor industry’s exponential progress over the past two decades.
The chip currently aboard NASA’s most capable planetary spacecraft, the kind that landed Curiosity and Perseverance on Mars, is the RAD750, first introduced in 2001 and based on architecture developed in the 1990s. It operates at up to 200 megahertz and delivers approximately 400 million instructions per second. A modern smartphone processor runs at 3 to 4 gigahertz and delivers hundreds of billions of operations per second. The gap between what a Mars rover carries in its computing brain and what a typical person carries in their pocket is measured in orders of magnitude.
That gap has been tolerable for traditional spacecraft operations, pointing instruments, managing power, and executing pre-programmed command sequences. It is not tolerable for the generation of missions now being planned. Autonomous landing on planetary surfaces with unknown terrain, real-time analysis of scientific data to identify anomalies worth investigating, coordinated operation of multiple spacecraft without ground control oversight, and support for human crews in deep space who cannot wait 40 minutes for a round-trip communication, all of these require computational capability that current space-grade chips cannot provide.
What the HPSC Actually Is
The HPSC processor is a system-on-a-chip, meaning it integrates the essential components of a complete computer — central processing units, memory, networking interfaces, input/output controllers, and computational offload engines into a single compact package that can fit in the palm of a hand.
It was developed through a commercial partnership between NASA’s Jet Propulsion Laboratory and Microchip Technology, a semiconductor company headquartered in Chandler, Arizona. The commercial partnership model is significant: rather than developing the chip entirely in-house, NASA worked with an established semiconductor manufacturer that could bring commercial-scale design and manufacturing expertise to a radiation-hardening challenge. Early access samples have already been provided to partners in the defense and commercial aerospace industries, suggesting that the technology’s applications extend well beyond NASA’s own mission portfolio.
The processor is designed as a multicore system, meaning it contains multiple independent processing units that can operate simultaneously on different tasks. Current space processors are predominantly single-core, handling one computation thread at a time. The multicore architecture of the HPSC enables parallel processing, running an autonomous navigation algorithm on one core while simultaneously processing scientific sensor data on another, managing communications on a third, and monitoring spacecraft health on a fourth. For AI workloads in particular, parallel processing is essential: the neural network computations that underpin modern AI applications are fundamentally parallel in nature and perform poorly on single-core architectures.
“Building on the legacy of previous space processors, this new multicore system is fault-tolerant, flexible, and extremely high-performing,” said Eugene Schwanbeck, program element manager in NASA’s Game Changing Development program at Langley Research Center. The fault-tolerant description is the critical qualifier: the HPSC maintains radiation hardening across its multicore architecture, which is considerably more challenging to achieve than in a single-core design and represents the primary technical breakthrough that makes the performance numbers meaningful rather than theoretical.
The full technical announcement from NASA’s official news release describes the chip’s architecture and the specific testing program being conducted at JPL, including the radiation, thermal, and shock exposure tests designed to validate performance against the conditions of deep space.
What Autonomous Spacecraft Actually Means
The phrase autonomous spacecraft is used frequently in coverage of the HPSC without much explanation of what it means in practice or why it matters for the future of space exploration.
The current model of spacecraft operation is fundamentally Earth-centric. Mission controllers on the ground plan every significant action the spacecraft will take, encode those plans as command sequences, uplink them to the spacecraft, and wait for the spacecraft to execute and report back. For missions in the inner solar system, Earth orbit, the Moon, and nearby asteroids — this works acceptably. For missions to Mars, Saturn, or beyond, the communication delays make it increasingly impractical. A spacecraft orbiting Mars faces a one-way communication delay of between 3 and 22 minutes, depending on the relative positions of Earth and Mars. A spacecraft descending to the Martian surface reaches the ground in about seven minutes. The entire landing sequence happens faster than a signal from Earth could even reach the spacecraft, let alone transmit instructions and receive a response. Everything that happens during entry, descent, and landing must be handled autonomously.
The HPSC is designed to extend that autonomous capability from a narrow set of pre-programmed landing sequences to a much broader range of real-time decision-making. A spacecraft equipped with the HPSC and appropriate AI software could detect an unexpected obstacle during landing and autonomously select an alternative touchdown site. It could identify a scientifically interesting geological feature during a flyby and autonomously reprioritize its observation schedule. It could detect a hardware anomaly and autonomously implement a diagnostic and recovery procedure without waiting for human intervention, which could take hours or days to arrive.
For crewed missions to the Moon and Mars, the stakes of autonomous capability are even higher. Astronauts on the lunar surface cannot wait 2.6 seconds for a response from Earth every time they need a decision supported. Astronauts on the Martian surface, facing communication delays of up to 22 minutes in each direction, need onboard systems capable of managing complex situations across timescales where Earth control is operationally irrelevant. The same trend toward AI systems making complex operational decisions that is visible in enterprise software deployment is now arriving in the most demanding operating environment that exists, as the broader shift toward autonomous AI systems reshaping how complex tasks are managed extends from factory floors and business departments to deep space.
The Scientific Data Problem
Autonomous decision-making is the most dramatic application of the HPSC, but a second application may prove equally consequential for the pace of scientific discovery: onboard data processing.
Current deep-space spacecraft collect vastly more data than they can transmit to Earth. The bottleneck is bandwidth. Radio communications across hundreds of millions of miles of space are constrained by the laws of physics in ways that no engineering ingenuity can fundamentally overcome. The data rate between Earth and a spacecraft at Mars ranges from a few hundred kilobits per second to a few megabits per second, depending on antenna size and alignment. A spacecraft equipped with high-resolution cameras and an array of scientific instruments can generate data at rates orders of magnitude higher.
The current solution is data compression and prioritization: instruments are designed to collect less data than they could, or scientists specify in advance which data to downlink and which to discard. Both approaches mean that scientific information is routinely lost because it cannot be transmitted. With a processor powerful enough to run AI-based classification algorithms in real time, a spacecraft could analyze its own data before transmission, intelligently identify the most scientifically significant observations, and prioritize those for downlink while discarding or heavily compressing lower-value data. The result is more science per bit of transmission bandwidth, a multiplier on the productivity of every mission that carries the chip.
For deep-space missions targeting the outer planets, the ice giants Uranus and Neptune, which have not been visited since Voyager 2 flew past them in the 1980s, the data transmission constraints are particularly severe. A spacecraft at Uranus faces communication delays of 2.5 hours and data rates measured in hundreds of bits per second. Onboard intelligence that can prioritize which of billions of instrument readings to transmit is not a convenience; it is a functional requirement for any meaningful science return from such missions.
The ScienceDaily coverage of the HPSC testing program describes in detail how the processor’s radiation-hardening approach addresses the specific failure modes that have limited previous attempts to bring high-performance computing to deep-space missions, and includes technical context on the testing conditions designed to simulate the particle environment of interplanetary space.
Beyond NASA: Defense, Aviation, and Automotive
The HPSC is being developed as a NASA technology, but its applications extend into adjacent industries that face similar requirements: high reliability, harsh environments, and the need for autonomous decision-making in situations where human intervention is impractical or impossible.
Microchip Technology is already adapting the HPSC architecture for aviation and automotive applications. Radiation hardening is less extreme a requirement in Earth’s atmosphere than in deep space, but the demand for fault-tolerant computing that handles errors gracefully without system failure is shared across industries where software crashes are not recoverable failures. An autopilot system that crashes at 35,000 feet, an autonomous vehicle controller that fails on a highway, and a spacecraft computer that fails during lunar orbit insertion are different in scale but similar in the fundamental requirement that the computing system must be designed to handle errors rather than simply assuming they will not occur.
The defense applications may be the most immediately significant. Hypersonic weapons, autonomous drones, and satellite-based intelligence systems all require computing capability that combines high performance with the ability to operate in electromagnetic and radiation environments that commercial processors cannot tolerate. Early access to HPSC samples has already been provided to partners in the defense industry, and the processor’s specifications appear designed with dual-use applications in mind. This dual-use dimension connects the HPSC to broader competitive dynamics in which the race for strategic orbital and space-based infrastructure is increasingly driven by computing capability as much as launch capacity.
What Happens Next
Testing at JPL will continue for several months, covering the full battery of radiation, thermal, shock, and functional validation required for spaceflight certification. Once certified, NASA plans to incorporate the HPSC into a range of platforms: Earth orbiters, planetary rovers, crewed habitats, and deep-space spacecraft. The first missions to fly the processor are expected to be announced as the certification process progresses.
The timeline for seeing the HPSC on an operational mission is measured in years rather than months — space hardware development and certification is a slow and deliberately conservative process. But the testing that has already been completed represents a significant milestone: demonstration that a radiation-hardened processor can achieve the kind of performance levels that AI workloads actually require, without compromising the reliability standards that space missions demand.
The broader implication is a shift in what space exploration can achieve at the frontier of the solar system. Missions that are currently impractical because of computing limitations, such as extended autonomous rovers on Europa or Titan, long-duration crewed habitats on the lunar surface, and networked constellations of small spacecraft coordinating without ground control, become considerably more feasible with an onboard processor capable of running the AI algorithms that enable genuine autonomy. The same progression from human-supervised to machine-autonomous operation that is transforming manufacturing, logistics, and enterprise computing on Earth is arriving in space, with consequences for the pace of discovery that will take decades to fully unfold.
The JPL announcement of the HPSC testing program provides the official technical context for the project, including its relationship to NASA’s broader Game Changing Development program and the commercial partnership model that enabled the chip’s development at a pace and cost that NASA’s traditional in-house development approach could not have matched.
The autonomous robot era that is reshaping industries on Earth, where machines are increasingly navigating complex physical environments without human oversight, is about to extend its reach to environments where no human has ever set foot. The space chip that made that possible fits in the palm of a hand and sends its first message to the universe in the subject line of an engineer’s email.
